For purposes of clarity and consistency, the following terms as used throughout this text and the appended claims should be interpreted as follows:
The phrase “semiconductor wafer” should be broadly interpreted as encompassing any substrate on which a semiconductor device or other integrated device is manufactured. Such substrates may, for example, comprise silicon or germanium wafers (of various diameters), and/or wafers of compound substances such as InAs, InSb, InP, GaSb, GaP or GaAs. The term also encompasses non-semiconductor materials (such as sapphire) on which one or more layers of semiconductor material have been deposited, e.g., as in the manufacture of LEDs. The semiconductor device or other integrated device concerned may, for example, be an integrated circuit, (passive) electronic component, opto-electronic component, biological chip, MEMS device, etc. Such devices will generally be manufactured in large numbers on a given substrate, and will typically be laid out in a matrix arrangement on at least one of said major surfaces. This matrix arrangement is delimited by said network of scribelines.
The term “scribeline” (also sometimes referred to as a “scribelane”) should be interpreted as referring to a (real or abstract) line extending along said major surface of the wafer, along which line the wafer is (ultimately) to be severed. In the case of a processed semiconductor wafer, a scribeline will generally lie in a “street” that extends between neighboring rows of integrated devices on the wafer, along which street the wafer is to be “diced” so as to allow separation of the devices in question. This procedure is conventionally referred to as “singulation”.
The term “network” should be broadly interpreted as encompassing regular and non-regular repetitive configurations. For example, some wafers may comprise a regular matrix of identical integrated devices separated from one another by scribelines forming a regular orthogonal network. On the other hand, other wafers may comprise devices of different sizes, and/or located at non-regular pitches with respect to one another, implying a correspondingly irregular configuration of scribelines.
These points will be discussed in more detail below.
Silicon semiconductor wafers are conventionally of the order of about 0.8 mm thick. Recently, semiconductor manufacturers have started to investigate the possible use of “thin” wafers, which will here be defined as wafers having a thickness T<200 μm, e.g., with T in the range 30-120 μm, or even less. Such thin wafers have various promising applications, such as:
In manufacturing stacked memories. In this case, use of a thin wafer means that more memory chips can be stacked within a given vertical space.
In manufacturing processors. In this case, use of a thin wafer may allow more efficient heat dissipation from an active processor device through its underlying substrate (a portion of the wafer) and into an adjacent heat sink.
The use of a thinner wafer may also contribute to: cost reduction, due to the use of less substrate material and less filler material (e.g., copper) in so-called vias (i.e., connective passages) penetrating the wafer, and device speed increases, since a thinner substrate will generally support higher signal frequencies.
Unfortunately, the processing of thin wafers may involve associated problems. In particular, it has transpired that thin wafers may be difficult to singulate whilst maintaining an acceptable device yield. More specifically, the inventors have observed that if a thin wafer is mechanically singulated using a saw, many of the singulated devices emerge from the singulation process in a mechanically broken state. Furthermore, if a thin wafer is radiatively singulated using a laser beam, the singulated devices may emerge from the singulation process apparently intact but nevertheless weakened, because many of them go on to break and/or electrically fail during subsequent processing and/or usage.
Such setbacks are hampering the successful application of thin wafers in the semiconductor manufacturing industry.
Aspects of embodiments address these and other issues.